The present disclosure relates to memory testing, and more specifically, to memory testing with selective use of an error correction code decoder. Errors in a memory cell of a computing system may be caused by a manufacturing defect, degradation over time, breakage, electrical or magnetic interference, etc. Redundant memory cells may be used to record parity and enable detection of errors. However, parity checking may detect limited types of errors (e.g., single-bit errors), leaving other errors undetected. A suite of test patterns may be developed to detect various types of errors. For example, a first test pattern may include all 0s, a second test pattern may include all 1s, etc. The first test pattern may be written to the memory cell and then a value may be read back from the memory cell. An error in the memory cell may be detected when the value and the first test pattern do not match. When an error is not detected, memory testing may continue by writing the rest of the test patterns in the suite to the memory cell in turn. However, using test patterns may require that the computing system be offline during memory testing.